System-on-a-chip (SoC) clock management - a scalable clock distribution approach

ABSTRACT

System and method for providing clocks to digital circuitry with a need for multiple clocks. A preferred embodiment comprises an oscillator controller (oscillator clock domain block  305 ) distributes a system clock generated by an oscillator to a plurality of clock domain blocks (GSM clock domain block  310  and so forth). The clock domain blocks use the system clock to generate specific clocks needed by attached hardware. The clock domain blocks may be programmed after manufacture to permit customized clock generation to meet requirements.

TECHNICAL FIELD

[0001] The present invention relates generally to digital circuitry, andmore particularly to a system and method for providing clocks to digitalcircuitry with a need for multiple clocks.

BACKGROUND

[0002] In many of today's high technology applications, a completesystem can be placed onto a single piece of silicon. The system on achip (SoC) may include all of the needed electronic circuits and partsfor a complete system onto a single integrated circuit (IC). Forexample, a SoC implementation of a cellular telephone may include aradio frequency transceiver, an analog-to-digital converter (ADC), adigital-to-analog converter (DAC), a microprocessor, memory, audioinput/output circuitry, display circuitry, battery management circuitry,peripheral interface circuitry, a clock distribution system, and soforth.

[0003] In a 3rd generation (3G) cellular telephone, such as onecompliant to the Universal Mobile Telephony System (UMTS) technicalstandard, the cellular telephone feature the ability to operate inmultiple different technical standards and have the ability to connectto other electronic devices via wired and wireless technology. Forexample, an UMTS cellular telephone also features the ability tocommunicate using global system for mobile communication (GSM) andwideband code-division multiple access (WCDMA), both of which havedifferent requirements. Furthermore, the UMTS cellular telephone mayfeature communications interfaces, such as universal serial bus (USB),variants of IEEE 802.11, and Bluetooth, to allow it to connect tocomputers and other electronic devices. These features are often calledconnectivity applications.

[0004] Each of these applications, since most of them operate atdifferent clock frequencies, will require a different clock in order tooperate. Therefore, the SoC implementation of the UMTS cellulartelephone may require a clock generator for each of the applications.When combined with time-to-market and cost constraints, many clockgeneration solutions for a SoC tends towards a operable solution, i.e.,a clock generation solution that provides the many different clocksneeded.

[0005] One easily implemented solution is to use a separate clockgeneration circuit for each application that needs a different clock.Since in many cases, the designers would already have an existing designfor each of the needed clocks, this solution would simply combine all ofthe needed clocks onto the integrated circuit.

[0006] One disadvantage of the prior art is that the use of anunoptimized clock generation circuit can lead to a clock generationcircuit that in needlessly complex and may require the use of multipleclock trees that need to be managed concurrently. This can result in alarge and cumbersome clock generation circuit that consumes more spaceon the integrated circuit than needed.

[0007] A second disadvantage of the prior art is that the use of anunoptimized clock generation circuit is that the clock generationcircuit may not efficiently power-down when the system is powered down.This can result in greater power consumption than necessary and hurtingbattery life if the system is a wireless device.

SUMMARY OF THE INVENTION

[0008] These and other problems are generally solved or circumvented,and technical advantages are generally achieved, by preferredembodiments of the present invention which provides a system and methodfor generating multiple clocks for an electronic system that may beintegrated onto an integrated circuit.

[0009] In accordance with a preferred embodiment of the presentinvention, a method for clock management comprising determining a needfor a clock signal, enabling a clock generator for the clock signal,wherein the clock generator is programmed to generate the clock signal,and using the clock generator to generate the clock signal.

[0010] In accordance with another preferred embodiment of the presentinvention, a clock management system comprising an oscillator controllercoupled to an oscillator, the oscillator controller containing circuitryto enable the operation of clock domain blocks coupled to the oscillatorcontroller and to distribute a clock signal generated by the oscillator,and a plurality of clock domain blocks coupled to the oscillatorcontroller, each clock domain controller containing circuitry togenerate a clock signal as specified in a configuration of the clockdomain controller based on a clock signal provided by the oscillatorcontroller.

[0011] In accordance with another preferred embodiment of the presentinvention, a mobile telephone comprising an analog processing hardwareblock coupled to an radio frequency (RF) transceiver, the analogprocessing hardware block containing circuitry to amplify, filter, andgain control a signal provided by the RF transceiver, a digitalprocessing hardware block coupled to the analog processing hardwareblock, the digital processing hardware block containing circuitry toerror detect and correct, filter, and decode a signal provided by theanalog processing hardware block, a processor coupled to the digitalprocessing block, the processor to execute programs to manipulate dataprovided by the digital processing hardware block, an applicationshardware unit coupled to the processor, the applications hardware unitcontaining circuitry to support different communications protocolssupported by the mobile telephone, a peripherals interface coupled tothe processor, the peripheral interface containing circuitry totranslate signals and protocols to allow the mobile telephone tocommunicate with attached devices, and a clock hardware unit coupled tothe processor, applications hardware unit, and peripherals interface,the clock hardware unit to provide clocks of differing frequencies andformats.

[0012] An advantage of a preferred embodiment of the present inventionis that it permits the quick addition of optimized clock generators sothat integrated circuit space and power consumption can be minimizedwith a minimum design effort and maximizing re-use.

[0013] A further advantage of a preferred embodiment of the presentinvention is that clock sleep and wakeup is performed in hardware, sothat processor and device sleep time can be maximized since overheadassociated with sleeping and waking up is minimized (hardware sleep andwakeup functions typically will have less overhead than software sleepand wakeup functions). Hence, power consumption can be furtherminimized.

[0014] Yet another advantage of a preferred embodiment of the presentinvention is generic clock generator can be integrated onto theintegrated circuit, allowing the addition of new clocks in the future.

[0015] The foregoing has outlined rather broadly the features andtechnical advantages of the present invention in order that the detaileddescription of the invention that follows may be better understood.Additional features and advantages of the invention will be describedhereinafter which form the subject of the claims of the invention. Itshould be appreciated by those skilled in the art that the conceptionand specific embodiment disclosed may be readily utilized as a basis formodifying or designing other structures or processes for carrying outthe same purposes of the present invention. It should also be realizedby those skilled in the art that such equivalent constructions do notdepart from the spirit and scope of the invention as set forth in theappended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

[0016] For a more complete understanding of the present invention, andthe advantages thereof, reference is now made to the followingdescriptions taken in conjunction with the accompanying drawing, inwhich:

[0017]FIG. 1 is a diagram of an exemplary usage scenario for a mobiletelephone;

[0018]FIG. 2 is a diagram of an exemplary mobile telephone which hasbeen integrated onto a single integrated circuit;

[0019]FIG. 3 is a diagram of a clock generation system for a mobiletelephone, according to a preferred embodiment of the present invention;

[0020]FIG. 4 is a diagram of a detailed view of a clock domain block,according to a preferred embodiment of the present invention;

[0021]FIG. 5 is a state diagram of a finite state machine used tocontrol the operation of a VCDG (VCTXO clock domain generator),according to a preferred embodiment of the present invention;

[0022]FIG. 6 is a state diagram of a finite state machine used tocontrol the operation of a clock domain block, according to a preferredembodiment of the present invention;

[0023]FIG. 7 is a flow diagram illustrating the operation of a clockdomain block and its interactions with a VCDG; and

[0024]FIG. 8 is a diagram of a mobile telephone with clock generatingcircuitry, according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

[0025] The making and using of the presently preferred embodiments arediscussed in detail below. It should be appreciated, however, that thepresent invention provides many applicable inventive concepts that canbe embodied in a wide variety of specific contexts. The specificembodiments discussed are merely illustrative of specific ways to makeand use the invention, and do not limit the scope of the invention.

[0026] The present invention will be described with respect to preferredembodiments in a specific context, namely a SoC implementation of amobile telephone compliant to the UMTS (Universal MobileTelecommunications System) technical standard. An overview of the UMTStechnical standard is provided in a document entitled “3^(rd) GenerationPartnership Project; Technical Specifications Group Services and SystemAspects General UMTS Architecture (Release 4),” which is hereinincorporated by reference. The invention may also be applied, however,to other mobile telephones compliant to other technical standards, aswell as integrated circuit applications wherein an efficient, flexible,and scalable clock generation circuit is needed.

[0027] With reference now to FIG. 1, there is shown a diagramillustrating an exemplary usage scenario 100 for a mobile telephone 105.The mobile telephone 105 is shown communicating with two different basestations 110 and 120, wherein the two base stations may be a part ofdifferent wireless communications networks using possibly differentcommunications technologies. The mobile telephone 105, when within aneffective coverage area of either of the two base stations 110 (coveragearea 110) and 120 (coverage area 125), can become linked with therespective base station and hence a part of the wireless communicationsnetwork. Note that although the base stations 10 and 120 are displayedas being in relatively close proximity, it may be possible that the basestations 10 and 120 are widely separated, perhaps cities (or states,countries, or continents) apart. It is the intent of FIG. 1 to displaythat the mobile telephone 105 may be capable of communicating witheither base station 110 and/or 120 when it is in the base station'scoverage area.

[0028] In addition to being able to communicate in a plurality ofdifferent wireless communications networks, the mobile telephone 105 maybe able to connect to one or more of many different types of devices 130via a connection 135. Note that while displayed as a wired connection,the connection 135 may be either a wired or a wireless connection. Forexample, the connection 135 may be wired, such as an universal serialbus (USB) connection, a Firewire connection, a serial port, a parallelport, a proprietary connection, and so forth or it may be wireless, suchas a Bluetooth connection, a variant of IEEE 802.11 connection, aninfrared connection, a light (or laser) emitting diode connection, andso on. The connection 135 may be thought of as providing short-rangeconnectivity to the device 130. Examples of devices may include but notlimited to computers, personal digital assistants,audio/video/multimedia appliances, telemetry equipment, and so on.

[0029] As integrated circuit fabrication technology has advanced, it hasbecome possible to place an entire electronic system, such as a mobiletelephone, onto a single integrated circuit (IC). This is commonlyreferred to as system-on-a-chip (SoC). The SoC may include all of theneeded electronic circuits and parts for a complete system onto a singleIC.

[0030] With reference now to FIG. 2, there is shown an exemplary mobiletelephone 200 which has been integrated onto a single IC 205. The figureprovides a high level view of the mobile telephone 200 and multipleapplications within the mobile telephone 200. For example, the mobiletelephone 200 may be an UMTS compliant wireless device (as shown by anUMTS application 210). An application may be a combination of hardwareand software needed to support a particular function.

[0031] However, the mobile telephone 200 may also be capable ofoperating in a GSM or WCDMA environment (applications 215 and 220). Inaddition to being capable of operating in different communicationsnetworks, the mobile telephone 200 can communicate with other devicesvia an USB interface (application 225), a Firewire interface(application 230), and a Bluetooth interface (application 235). Tofurther enhance the flexibility of the mobile telephone 200, the mobiletelephone 200 may include one (or more) custom applications 240 that maynot be determined at the time of integration, but can be programmed at alater date. For example, the owner of the mobile telephone 200 maydesire the ability to operate in standard CDMA (IS-95) communicationsnetworks. The owner may be able to purchase this and other differentcapabilities and applications from the service provider. Alternatively,the service provider may add certain features to the mobile telephone200 as part of a value added package.

[0032] Many of the different applications supported by the mobiletelephone 200 require clocks of differing frequencies. For example, USBuses a 48 MHz clock, while GSM uses a 13 MHz clock, and WCDMA a 15.36MHz clock. Therefore, a solution using a single clock generating circuitwould likely require a significant amount of design work andoptimization to provide good performance. Unfortunately, with time andcost constraints, the clock generation circuit may not receive theoptimization it requires. Additionally, the capability of supportingapplications not implemented during integration would likely prohibitperformance optimization for these custom applications and their clocks.

[0033] With reference now to FIG. 3, there is shown a clock generationsystem 300 for a mobile telephone, according to a preferred embodimentof the present invention. Note that although the clock generation system300 is designed for use in a mobile telephone, it is flexible enough tobe used in a wide variety of integrated systems which have a need formultiple clocks. Since the figure illustrates a clock generation systemfor use in a mobile telephone, the terms used will be focused on amobile telephone. However, the use of mobile telephony terms should notbe construed as limiting the possible uses for the present invention.

[0034] Central to the clock generation system 300 is a VTCXO(voltage/temperature controlled crystal oscillator) clock domaingenerator (VCDG) 305. According to a preferred embodiment of the presentinvention, the VCDG 305 can be a dedicated state machine (a finite statemachine) that can be enabled during a power-on sequence of the mobiletelephone and used to control each of a plurality of individual clockdomain blocks (such as a GSM clock domain block 310, a WCDMA clockdomain block 315, a dual mode (D.M.) clock domain block 320, i.e., onefor each of the applications in the mobile telephone). Clock domainblocks, sometimes referred to as system ultra-low-power devices, managea system clock provided by the VCDG 305 (for example, a 13 MHz clock)and distributes it to attached peripherals and/or modules. Note thatseveral clock domain blocks in FIG. 3 (namely a CPU clock domain block325 and custom clock domain block 330) are displayed as not beingconnected to the VCDG 305). This is only to maintain simplicity in thefigure. In an actual implementation, these clock domain blocks andothers would be connected in a fashion that is consistent with the GSMclock domain block 310, the WCDMA clock domain block 315, and the dualmode clock domain block 320.

[0035] The VCDG 305 can be used to provide timing information as well ascontrol signals to the individual clock domain blocks. According to apreferred embodiment of the present invention, to each one of theindividual clock domain blocks, the VCDG 305 can be used to provide asystem clock signal (“SYS_CLK13M”), a system reset signal (“SYS_NRST”),and a wakeup signal (“CLR_DEEP_SLEEP”). Additionally, the VCDG 305 maybe responsible for controlling a VTCXO (not shown) to which it can beattached. The VTCXO may be used to provide a system reference clockusually tightly controlled and tuned during network operation. Forexample, a 13 MHz system clock. Furthermore, the VCDG 305 may controlglobal enables for certain portions of the mobile telephone, such as aradio frequency (RF) portion, a data slicer portion, and the VCTXOitself. The VCDG 305 may also receive several input control signals,including a sleep signal, a wakeup signal, a reset signal, and an enablesignal for the system reference clock.

[0036] From each of the individual clock domain blocks, several controlsignals may be provided to the VCDG 305. One such control signal may bea sleep signal that may be used to indicate that the clock domain blockasserting such a signal is placing itself in sleep mode. An AND gate 350can be used to combine the sleep signal from each of the clock domainblocks, along with a signal asserted by a global deep sleep block 345.If all clock domain blocks are asserting the sleep signal as well as theglobal deep sleep block 345, then the VCDG 305 may itself be placed insleep mode. This assures that the VCDG 305 will not enter sleep modeunless all of the clock domain blocks dependent upon it are themselvesin sleep mode and if the mobile telephone is also in sleep mode.

[0037] Another control signal that may be asserted by the clock domainblocks is a wakeup signal. The wakeup signal may be asserted by a clockdomain block when it desires to wakeup from sleep mode. The mobiletelephone may also assert a wakeup signal (via a software wakeup block335). The wakeup signals from the clock domain blocks and the softwarewakeup block 335 may be combined via an OR gate 340 and provided to theVCDG 305, assuring that if one or more of the clock domain blocks (orthe mobile telephone) is waking up, then the VCDG 305 will also be wokenup.

[0038] With reference now to FIG. 4, there is shown a diagramillustrating a detailed view of a clock domain block, according to apreferred embodiment of the present invention. The clock domain blockdisplayed in FIG. 4 may be a clock domain block that is capable of beingprogrammed (customized) for operation for a specific application, suchas the custom clock domain control block 330 displayed in FIG. 3. Afterbeing programmed for a specific application, such as GSM, the clockdomain block 400 may appear like the GSM clock domain block 310 (FIG.3).

[0039] According to a preferred embodiment of the present invention, theclock domain block 400 may include four specific memory locations (orregisters). The information stored in the four specific memory locationsmay be used by a finite state machine 425 to control the operation ofthe clock domain block 400. Note that while being describe as specificmemory locations, the four memory locations may be one or more bits in asingle memory location and the bit (or group of bits) can be used tostore the contents of the specific memory location. This means that asingle memory location, for example, a 16-bit word may be used to storethe contents intended for the four specific memory locations. Accordingto a preferred embodiment of the present invention, the contents of eachof the four specific memory locations can be stored in a single 16-bitword of memory, along with a current state of the clock domain block'sfinite state machine (which will be described below).

[0040] A first memory location, referred to as an enable 405, may beused as an asynchronous reset of the finite state machine of the clockdomain block 400. For example, if the enable 405 is false (perhapsstoring a binary zero (0)), then the finite state machine 425 can undergo a reset, and if the enable 405 is true (perhaps storing a binary one(1)), then the finite state machine 425 can be enabled and ready foroperation. A second memory location, referred to as a deep sleep 410,may be used generate a deep sleep request that is to be transmitted tothe VCDG 305. For example, if the deep sleep 410 is false (binary zero(0)), then a deep sleep request will not be generated, and if the deepsleep 410 is true (binary one (1)), then a deep sleep request will begenerated and transmitted.

[0041] A third memory location, referred to as a wakeup processor 415,may be used as a mask of an interrupt sent to the processor (not shown)after a clock request has been sent by circuitry attached to the clockdomain block to the clock domain block. For example if the wakeupprocessor 415 is false, then the interrupt to the processor isgenerated, and if the wakeup processor 415 is true, then the interruptto the processor is masked. A fourth memory location, referred to as asoft wakeup 420, may be used to store a wakeup request that is to betransmitted to the VCDG 305 in the form of a clock request. For example,if the soft wakeup 420 is false, then a soft wakeup is not generated,and if the soft wakeup is true, then a soft wakeup will be generated andtransmitted.

[0042] With reference now to FIG. 5, there is shown a diagramillustrating a state diagram 500 of a finite state machine used tocontrol the operation of a VCDG (such as the VCDG 305 (FIG. 3)),according to a preferred embodiment of the present invention. Uponpower-up or after a reset, the finite state machine (FSM) controllingthe VCDG 305 in state “Auto Wakeup” 505, where it can evaluate thestatus of auto wakeup. Note that the status check may be only evaluatedonce when the VCDG 305 is enabled. If auto wakeup is true, then the VCDG305 may be able to automatically wakeup when receives a signal.

[0043] After checking the status of auto wakeup, the FSM transitions tostate “Deep Sleep” 510, where it remains as long as does not receive awakeup request (NWAKEUP_REQ=1). When in “Deep Sleep” 5 10, the VCDG 305and attached clock domain blocks may essentially be in a turned off(disabled) mode, wherein no clocks are being generated. However, deepsleep can be different from powered off mode in that wakeup from deepsleep can be more rapidly achieved. While in state “Deep Sleep” 510, theFSM may receive signals telling it to start VTCXO operation and/or areset signal (NRST) or a power on signal (PWRON).

[0044] When the FSM receives either a reset request for one or more ofthe clock domain blocks (ULPD_SYS_NRST=0 (a true value)) or a wakeuprequest (NWAKEUP REQ=0 (a true value)), then the FSM may transition tostate “Load RF” 515. While in “Load RF” 515, the VCDG 305 may beprovided with a number of clock cycles to wait prior to enabling a radiofrequency portion of the mobile telephone. This wait, specified with avalue “Setup” that specifies a number of clock cycles, can permit clockssufficient time to stabilize. If the wait (as specified by the value“Setup”) is greater than zero, then the FSM may transition to state “DecRF” 520 wherein it decrements “Setup” once per clock cycle until “Setup”is equal to zero wherein the FSM may then transition to state “LoadVTCXO” 525. If “Setup” was equal to zero when the FSM was in state “LoadRF” 515, then the FSM may automatically transition to state “Load VTCXO”525.

[0045] In state “Load VTCXO” 525, the FSM may once again be placed intoa waiting state while the VTCXO is permitted to become stable. In the“Load VTCXO” state 525, the wait (again specified by a value “Setup”) isprovided to the VCDG 305 and if “Setup” is greater than zero, the FSMmay transition to state “Dec VTCXO” 530 where it will decrement a numberof clock cycles equal to “Setup” to permit the VTCXO sufficient time tostabilize. If “Setup” is equal to zero when the FSM is in state “LoadVTCXO” 525, the FSM may automatically transition to state “Load Slicer”535. The “Load Slicer” state 535 is similar to the states “Load RF” 515and “Load VTCXO” 525, wherein the VCDG 305 is forced to wait a specifiednumber of clock cycles to allow the slicer (not shown) to become stable.Similarly, a state “Load Clk13” 545 can be used to force the VCDG 305 towait until the Clk13 (a 13 MHz clock) to become stable.

[0046] Finally, the FSM can enable Clk13 (note that Clk13 may beparticular to this implementation of the VCDG 305 and a clock of adifferent frequency may be used in other implementations) in state“Enable Clk13” 555. After enabling Clk13, the FSM awakens the VCDG 305and puts it in operation. As long as the FSM does not receive a deepsleep request (DEEP_SLEEP₁₃ REQ=0) and a negative wakeup request remainsinactive (NWAKEUP_REQ=0), the FSM keeps the VCDG 305 operating. However,if the FSM should receive a deep sleep request (DEEP_SLEEP_REQ=1) and anegative wakeup request becomes active (NWAKEUP_REQ=1), then the FSM maytransition to state “Disable Clk13” 565 wherein the Clk13 can becomedeactivated. Should the FSM continue to receive an active negativewakeup request (NWAKEUP_REQ=1) while in state “Disable Clk13” 565, theFSM can transition to state “Deep Sleep” 510 wherein it can place theVCDG 305 into a deep sleep mode. If while in state “Disable Clk13” 565and the FSM receives an inactive negative wakeup request(NWAKEUP_REQ=0), then the FSM can reactivate the Clk13 (state “EnableClk13” 555) to resume operation of the VCDG 305.

[0047] With reference now to FIG. 6, there is shown a diagramillustrating a state diagram 600 of a finite state machine used tocontrol the operation of a clock domain block, according to a preferredembodiment of the present invention. As in the case of the FSM for theVCDG 305 (discussed above), the FSM for a clock domain block begins byevaluating the status of auto wakeup in a state “Auto Wakeup” 605. Afterevaluating the status of auto wakeup, the FSM can transition to a “DeepSleep” state 610, wherein the clock domain block may essentially be in asleep mode. In addition to entering “Deep Sleep” state 610 from theevaluation of auto wakeup, the FSM may enter “Deep Sleep” state 610 ifit receives a VTCXO negative reset (VTCXO_UPLD_NRST) or a softwareenable (SOFT_UPLD_EN).

[0048] While in “Deep Sleep” state 610, the FSM may transition to state“Wait VTCXO” 615 if it receives one or more of the following: a negativesystem reset inactive (SYS_NRST=0) or an active Clk13 request(CLK13M_REQ=1) or an active software wakeup (SOFT_WAKEUP_REQ=1). Whilein state “Wait VTCXO” 615, the FSM waits until it receives a signal fromthe VCDG 305 to allow the clock domain block to begin operating. TheVCDG 305 asserts an active clear deep sleep signal (CLEAR_DEEP_SLEEP=1)to enable the FSM to transition into a “En Clk13M” state 620, whereinthe FSM can enable its reception of the Clk13 from the VCDG 305. The FSMcan then transition into an “Awake” state 625, where it can generate aclock as per its configuration.

[0049] When in the “Awake” state 625, the FSM can be placed into a deepsleep mode if it receives an inactive soft wakeup signal(SOFT_WAKEUP_REQ=0) and an inactive Clk13 signal (CLK13M_REQ=0) and anactive deep sleep signal (SOFT_DEEP_SLEEP=1) signal from the VCDG 305.With the reception of these three signals, the FSM can transition to a“Switch 13M 32K” state 630 wherein the FSM can switch from the 13 MHzclock to a lower frequency clock (in this case a 32 KHz clock, however,this particular frequency is implementation dependent). After switchingto the lower frequency clock, the FSM may enter the “Deep Sleep” state610 where it shuts down, waiting to be reawaken.

[0050] With reference now to FIG. 7, there is shown a flow diagram 700illustrating the operation of a clock domain block and its interactionswith a VCDG, according to a preferred embodiment of the presentinvention. The operation of the clock domain block may begin when itfirst determines that there is a need for a clock of the type that theclock domain block has been configured to provide (block 705), forexample, a clock (or set of clocks) required for GSM operation. If thereis no determined need for a clock, then the clock domain block may beable to remain in sleep mode (block 735). With the need for a clock, theclock domain block can transmit a request to the VCDG to enable theclock domain block to begin generating the needed clock (block 710).

[0051] If the VCDG was not in a sleep mode (block 715) when the requestwas received, the VCDG can enable the clock domain block (block 720) tobegin generating the needed clock. If the VCDG was in a sleep mode whenthe request was received, the clock domain block may need to wait forthe VCDG to wakeup (block 725) and once the VCDG wakes up, the VCDG canenable to clock domain block (block 720) to begin generating the neededclock. Once the VCDG has enabled the clock domain block to generate theneeded clock, the clock domain block can make use of its configurationto generate the needed clock. Hence, through different configurations,the same design for a clock domain block can be used to generate a widevariety of different clocks.

[0052] The clock domain block may continue generating the clock until itdetermines that there is no longer a need for the clock (block 730).When there is no longer a need for the clock that the clock domain blockis generating, then the clock domain block can place itself into a sleepmode (block 735) and send a signal to the VCDG to help put the VCDG intoa sleep mode if the VCDG is not busy with other clock domain blocks.

[0053] With reference now to FIG. 8, there is shown a diagramillustrating a high level view of a SoC implementation of a wirelesstelephone 800, according to a preferred embodiment of the presentinvention. The wireless telephone 800, as implemented on a singleintegrated circuit, may include a radio frequency (RF) hardware 805which may be responsible for receiving and transmitting informationover-the-air. The RF hardware 805 may be coupled to analog processinghardware 810. The analog processing hardware 810 can be used to filter,amplify, flatten, gain control, and so forth the signals received by theRF hardware 805 to make the signals ready for processing by circuitry inthe remainder of the wireless telephone 800. The analog processinghardware 810 may also be used for transmission of signals as well. Whenso used, the analog processing hardware 810 may be used to provideamplification and filtering of the signals to be transmitted.

[0054] An analog-to-digital converter (ADC) 815 can be used to convertoutput from the analog processing hardware 810 into a digital symbolstream which can be processed by digital processing hardware 820. Thedigital processing hardware 820 may be perform operations such as errordetecting and correcting, decoding, deinterleaving, despreading, digitalfiltering, and so forth on the digital symbol stream provided by the ADC815. When used in transmission operations, the digital processinghardware 820 may be used perform operations such as encode, spread,interleave, and so forth on a digital data stream provided by aprocessor 825.

[0055] The processor 825 (or a digital signal processor (DSP) or acontroller) operates as a central brain of the wireless telephone 800.The processor 825 may be used to perform additional operations on thedata received or to be transmitted. The processor 825 may also be usedto control the operation of additional hardware present in the wirelesstelephone 800 to provide additional functionality. Attached to theprocessor 825 is a memory 830 that can be used for storage of data,programs, intermediate processing results, and so forth.

[0056] Application hardware 840, used to provide additionalfunctionality to the wireless telephone 800, such as multi-modeoperation, multi-media functionality, general purpose computing,additional connectivity (such as USB, Firewire, and so on), and so forthmay be coupled to the processor 825 and memory 830. Finally, if thewireless telephone 800 has the capability to accept peripherals such asdisplays, audio/video output/input, information/data input, and others,a peripheral interface 835 may be present to provide necessary protocoland data compatibility conversions.

[0057] A clock hardware unit 850, such as one described above, may beused to provide the different clocks needed by the different hardwareunits. For example, the processor 825 may require a clock of differentfrequency and duty cycle from the application hardware 840 supportingthe different applications and from the hardware in the peripheralinterface 835.

[0058] Note that FIG. 8 illustrates the use of the present invention toprovide a flexible and scalable clock management system for a mobiletelephone that has been integrated into an integrated circuit. However,the present invention may be used to provide a flexible and scalableclock management system for a wide variety of systems that have a needfor multiple clocks of different frequencies and formats. For example, acomputer, a personal digital assistant, a multimedia playback device,telemetry equipment, and so forth.

[0059] Although the present invention and its advantages have beendescribed in detail, it should be understood that various changes,substitutions and alterations can be made herein without departing fromthe spirit and scope of the invention as defined by the appended claims.

[0060] Moreover, the scope of the present application is not intended tobe limited to the particular embodiments of the process, machine,manufacture, composition of matter, means, methods and steps describedin the specification. As one of ordinary skill in the art will readilyappreciate from the disclosure of the present invention, processes,machines, manufacture, compositions of matter, means, methods, or steps,presently existing or later to be developed, that perform substantiallythe same function or achieve substantially the same result as thecorresponding embodiments described herein may be utilized according tothe present invention. Accordingly, the appended claims are intended toinclude within their scope such processes, machines, manufacture,compositions of matter, means, methods, or steps.

What is claimed is:
 1. A method for clock management comprising:determining a need for a clock signal; enabling a clock generator forthe clock signal, wherein the clock generator is programmed to generatethe clock signal; and using the clock generator to generate the clocksignal.
 2. The method of claim 1 further comprising after thedetermining, transmitting a request to an oscillator controller toenable the clock generator for the clock signal.
 3. The method of claim1, wherein the determining comprises receiving a wakeup request from anelectronic device needing the clock signal.
 4. The method of claim 3,wherein the electronic device is a peripheral.
 5. The method of claim 1further comprising after the using: receiving a sleep request;terminating the generation of the clock signal by the clock generator;and sending a sleep request to an oscillator controller.
 6. The methodof claim 5, wherein there are a plurality of clock generators, andwherein upon receiving the sleep request from the clock generator, ifthere are no other clock generators generating clock signals, theoscillator controller can enter a sleep mode.
 7. The method of claim 5,wherein the sleep request is from an electronic device.
 8. The method ofclaim 7, wherein the electronic device is the same electronic devicethat needed the clock signal.
 9. The method of claim 1 wherein there area plurality of clock generators, and each clock generator can beprogrammed to generate a different clock signal.
 10. The method of claim1 further comprising after the determining, waking up an oscillatorcontroller with a wakeup request if the oscillator controller is in asleep mode.
 11. The method of claim 10, wherein the wakeup request is asoftware generated wakeup request.
 12. The method of claim 10, whereinthe wakeup request is a signal on a wakeup request line coupled to theoscillator controller
 13. The method of claim 10 further comprisingafter the determining, transmitting a request to an oscillatorcontroller to enable the clock generator for the clock signal, andwherein the wakeup request is automatically generated by the request tothe oscillator control.
 14. A clock management system comprising: anoscillator controller coupled to an oscillator, the oscillatorcontroller containing circuitry to enable the operation of clock domainblocks coupled to the oscillator controller and to distribute a clocksignal generated by the oscillator; and a plurality of clock domainblocks coupled to the oscillator controller, each clock domaincontroller containing circuitry to generate a clock signal as specifiedin a configuration of the clock domain controller based on a clocksignal provided by the oscillator controller.
 15. The clock managementsystem of claim 14, wherein each clock domain block is configured togenerate a different clock signal.
 16. The clock management system ofclaim 14, wherein at least one of the clock domain blocks may beconfigured after manufacture to generate a desired clock signal.
 17. Theclock management system of claim 14, wherein at least one of the clockdomain blocks may be configured during operation to generate a desiredclock signal.
 18. The clock management system of claim 14 furthercomprising a sleep circuit coupled to each of the clock domain blocksand a global sleep signal line, the sleep circuit to place theoscillator controller to sleep when the clock domain blocks and theglobal sleep signal line assert a specified value.
 19. The clockmanagement system of claim 14 further comprising a wakeup circuitcoupled to each of the clock domain blocks and a software wakeup signalline, the wakeup circuit to wakeup the oscillator controller when atleast one of the clock domain blocks and the software wakeup signal lineassert a specified value.
 20. The clock management system of claim 14,wherein there are at least three clock domain blocks, and wherein threeof the clock domain blocks are configured to generate clocks forUniversal Mobile Telephony System (UMTS), Global System for MobileTelephony (GSM), and Universal Serial Bus (USB) compliant hardware. 21.A mobile telephone comprising: an analog processing hardware blockcoupled to an radio frequency (RF) transceiver, the analog processinghardware block containing circuitry to amplify, filter, and gain controla signal provided by the RF transceiver; a digital processing hardwareblock coupled to the analog processing hardware block, the digitalprocessing hardware block containing circuitry to error detect andcorrect, filter, and decode a signal provided by the analog processinghardware block; a processor coupled to the digital processing block, theprocessor to execute programs to manipulate data provided by the digitalprocessing hardware block; an applications hardware unit coupled to theprocessor, the applications hardware unit containing circuitry tosupport different communications protocols supported by the mobiletelephone; a peripherals interface coupled to the processor, theperipheral interface containing circuitry to translate signals andprotocols to allow the mobile telephone to communicate with attacheddevices; and a clock hardware unit coupled to the processor,applications hardware unit, and peripherals interface, the clockhardware unit to provide clocks of differing frequencies and formats.22. The mobile telephone of claim 21, wherein the clock hardware unitcomprises: an oscillator controller coupled to an oscillator, theoscillator controller containing circuitry to enable the operation ofclock domain blocks coupled to the oscillator controller and todistribute a clock signal generated by the oscillator; a plurality ofclock domain blocks coupled to the oscillator controller, each clockdomain controller containing circuitry to generate a clock signal asspecified in a configuration of the clock domain controller based on aclock signal provided by the oscillator controller.
 23. The mobiletelephone of claim 22, wherein the applications hardware unit comprisesa Universal Mobile Telephony System (UMTS) unit, a Global System forMobile Telephony (GSM) unit, a Universal Serial Bus (USB) unit; andwherein the clock hardware unit contains clock domain blocks for eachlisted unit.
 24. The mobile telephone of claim 23, wherein the clockhardware unit contains a clock domain block that is customizable aftermanufacture to produce a desired clock signal.
 25. The mobile telephoneof claim 23, wherein the applications hardware unit further comprises aCDMA2000 (Wideband Code-Division Multiple Access) unit.
 26. The mobiletelephone of claim 21, wherein the mobile telephone is operable in aUniversal Mobile Telephony System (UMTS) compliant wireless network anda Global System for Mobile Telephony (GSM) compliant wireless network.